The present invention relates to a charge transfer device employing a charge coupled device (CCD) and, more particularly, to an improvement in a signal output stage thereof for detecting charges transferred from the CCD and for outputting a voltage level responsive thereto.
The signal output stage of a charge transfer device is, generally, equipped with a floating diffusion region formed in a semiconductor substrate. This region is supplied with and thus temporarily stores the transferred charges. In response to the charges thus stored, an output voltage level is derived representing the amount of the stored charges. Therefore, it is necessary to remove the charges stored in the floating region to reset the voltage level thereof each time the output voltage is derived.
To this end, a reset diffusion region is formed in the semiconductor substrate adjacently to the floating diffusion region. A reset gate electrode is formed over the part of the semiconductor substrate between the floating diffusion region and the reset diffusion region with intervention of a gate insulating film. The reset diffusion region is supplied with a certain reference voltage such as a power supply voltage of the device, and the reset gate electrode is supplied with a reset signal each time the output voltage is derived. The reset signal causes a channel region to be formed between the floating and reset regions, so that the charges stored in the floating region are transferred to and thus absorbed by the reset region.
In this case, in order to remove all the charges from the floating diffusion region to ensure the reset function, it is required to supply such a reset signal that induces a sufficient channel region under the reset gate electrode. For example, in a case where each of the floating and the reset diffusion regions is of an N-type, the potential well for electrons under the gate electrode must be deeper than that of the reset diffusion region. To this end, a reset signal having a sufficiently high level is needed. The reset signal is further recruited to be supplied with a high frequency. However, it is difficult to produce a reset signal satisfying both of a high frequency and a high voltage level. Therefore, some devices have been proposed to overcome the problems with the reset operation described above.
Referring to FIG. 1, there is shown one such improved device. This device is disclosed in Japanese Laid-Open Patent Application (Kokai) Sho 61-224357. FIG. 2 shows an graph of potential levels of electrons transferred in the device of FIG. 1. FIG. 3 shows a timing chart of the signals .phi.1, .phi.2 and .phi.R shown in FIG. 1. FIG. 4 shows a graph of voltages at portions of a surface of the semiconductor substrate 1 versus voltages of corresponding gate electrodes 4a, 4b, 5a, 5b, 6a and 6b. The device of FIG. 1 is a surface channel type CCD (SCCCD) wherein the charge transfer channel regions are selectively formed on a surface of a p-type semiconductor substrate 1 in response to voltage levels of the transfer electrode 4a, 4b, 5a and 5b supplied with the transfer control signals .phi.1 and .phi.2. The substrate 1 is supplied with a back bias voltage Vbs such as -2.5 V. A floating diffusion region 2 and a reset diffusion region 3 are of n-type and form a reset transistor TR of n-channel MOS type with a reset gate electrode 7. In this conventional device, the reset voltage to be supplied to the reset diffusion region 3 is generated by a cascade circuit having transistors T3 and T4 which is connected between the power supply voltage line VB, which voltage VB is 5 V for example, and a ground line GND and outputs an intermediate voltage V1 which is 3 V, for example, and lower than the power supply voltage VB. The intermediate voltage V1 is also supplied to the output gate electrodes 6a and 6b as shown in FIG. 1. The transfer control signals .phi.1 and .phi.2 and the reset signal .phi.R have an amplitude between the power supply voltage level VB and the ground voltage level GND as shown in FIG. 3.
In operation, at the time t1, the transfer control signals .phi.1 and .phi.2 and the reset signal .phi.R respectively become high, low and high levels so that the voltages of the surface portions under the gate electrodes 4a, 5a and 6a become 2.3 V and the voltages of the surface portions under the gate electrodes 4b, 5b and 6b become 4.5 V as shown in FIG. 4. Therefore, the potential levels of electrons at the each part of the surface of the semiconductor substrate 1 are brought into a reset state as shown in FIG. 2 by a dotted line. Since the voltage V1 of the reset diffusion region 3, that is 3 V as mentioned above, is set sufficiently lower than the voltage of the surface region under reset gate electrode 7, that is 4.5 V as mentioned above, the potential well W21 of the potential of electrons formed under the reset gate electrode 7 becomes deeper than the well W23 formed in the diffusion regions 3. Thus, the well W21 efficiently transfers the carriers in the potential well W22 in the floating diffusion region 2 to the well W23 in the reset diffusion region 3. Therefore, the potential level of the floating diffusion region 2 is reset and adjusted to a certain initial level determined by the potential level of the well W21.
At the time t2, that is when the reset signal .phi.R is at its low level, the floating diffusion region enters a floating state and maintains its initial level owing to parasitic capacitances of the pn junction between the region 2 and the semiconductor substrate 1. Subsequently, at the time t3, the potential levels of each part of the surface of the substrate 1 enters a transfer state as shown in FIG. 2 by a solid line and the carriers are transferred from the potential well W25 under the transfer gate 5b to the well W22 through the fixed potential area P21 under the output gate electrodes 6a and 6b. In this device, the output gate electrodes 6a and 6b bear a function to form the fixed potential area P21 which serves as a part of a potential slope for transferring the carriers to the well W21 at the time t3 and as a potential barrier for preventing reverse transfer of the carriers from the well W21 to the well W25. When the carriers are transferred to the floating diffusion region 2, the voltage level VFD of the floating diffusion region 2 is detected by the output circuit 01 as shown in FIG. 1 which outputs the signal OUT. Therefore, this device merely necessitates the reset signal R having a power supply voltage of the device, eliminating any circuit specialized in forming a high frequency reset signal having a high voltage.
Turning to FIG. 5, a device according to another prior art is shown therein. This device is disclosed in Japanese Laid-open Patent Application (Kokai) Hei 3-129744. FIGS. 6 and 7 show graphs of potentials of electrons of each part of the surface of the substrate shown in FIG. 5. According to FIG. 5, an n-type buried channel layer 12 having a low impurity concentration is formed on a surface of a semiconductor substrate 11, in which further formed are an n-type floating diffusion region 20 connected to a output circuit 50, an n-type reset diffusion region 21 connected to a capacitor C and an n-type absorb diffusion region 22 connected a voltage generator 23 for generating a constant high level voltage VG, that is 12 V. The surface of the buried channel layer 12 is covered with a gate insulating film 13 on which a reset gate electrode 17 supplied with a reset signal .phi.R and a barrier gate electrode 18 supplied with a power supply voltage VB, that is 5 V, are formed. The floating diffusion region 20, the reset diffusion region 21 and the reset gate electrode 17 form a reset transfer gate TRE and the reset diffusion region 21, the absorb diffusion region 22 and the barrier gate electrode 18 form a barrier transfer gate TBR as shown in FIG. 5. Transfer gate electrodes 14a, 14b, 15a and 15b are supplied with transfer control signals .phi.1 and .phi.2 in a similar manner as the device of FIG. 1. An output gate electrode 16 is supplied with a low level voltage VOG taking a level of about 1 V and sets a potential level of electrons in the region just below the output gate electrode 16 at the potential .psi.OG as shown in FIG. 6. A potential level .psi.B of electrons in the channel region of the barrier transfer gate TBR is determined by a potential level at the absorb diffusion region 22 and the voltage VB supplied to the barrier gate electrode 18. Since the barrier transfer gate TBR is constantly conductive in such a condition, the potential level .psi.RD at the reset diffusion region 21 is set to be equal to the potential .psi.B. A potential level of electrons in the channel region just below the reset gate electrode 17 is determined by a high or a low voltage of the reset signal .phi.R as shown in FIG. 6 wherein the potential according to the high level of the reset signal .phi.R is labeled .psi.R. In this device, since the channel region of the reset transfer gate TR is of n-type semiconductor region having a low impurity concentration, when the reset signal .phi.R is at a low level, the potential barrier B1 formed under the reset gate electrode 17 can be set high so as to prevent the transfer of the electrons therethrough and, at the same time, when the reset signal .phi.R is at a high level, the potential level .psi.R at the channel region under the reset gate electrode 17 can be decreased to a level lower than the potential .psi.RD as shown in FIG. 6 owing to a short channel effect in the reset transfer gate TRE. The electrons transferred to the reset diffusion region 21 are first stored in the capacitor C and then transferred to a deep potential well W61 formed at the absorb diffusion region 22 which is supplied with the high voltage VG of 12 V. The capacitor C which has a respectively large capacity is charged constantly according to the potential level .psi.RD and performs a function of maintaining the potential level .psi.RD at the reset diffusion region 21 stably when the electrons are transferred from the floating diffusion region 20 so as to complete the transfer of electrons from the floating diffusion region 20 safely. Therefore, in this device, the reset operation is achieved by using a reset signal .phi.R having its high level not larger than the power supply level of the device and, at the same time, owing to the deep potential well W61, the reset operation is performed certainly even under the condition of a low power supply level, such as 5 V or 3 V, so that the output operation is performed stably.
However, in the conventional device of FIG. 1, since the reset voltage V1 supplied to the reset diffusion region 3 is a intermediate voltage V1 which is lower than the power supply voltage VB, the reset operation necessitates a considerably long time. If the reset operation is performed at high speed, on the contrary, the floating diffusion region 2 is not discharged sufficiently so that the output signal level of the following cycle is disrupted.
In the device of FIG. 5, on the other hand, since the reset diffusion region 21 is connected to a large capacitance C so as to maintain the potential level .psi.RD by eliminating the potential change caused by the direct current to or from the reset diffusion region, a passing change in the power supply voltage VB causes a potential change .alpha. in the reset diffusion region 21 and the potential change .alpha. is maintained by the capacitor C, deteriorating the output property of the device for a considerably long time thereafter. That is, as shown in FIG. 6, once the change in power supply voltage VB, which is supplied to the barrier transfer gate electrode 18, causes the potential of the channel region of the barrier transfer gate TRB to change to the potential .psi.B+.alpha. at the time t1, the potential level .psi.RD at the reset diffusion region 21 is set to be equal to the same potential .psi.RD'=.psi.B+.alpha. as mentioned above. Then, at the time t2, after the power supply voltage VB is restored to the initial voltage level and the potential .psi.B+.alpha. is also restored to the potential .psi.B as shown in FIG. 7, since the potential barrier B2 is formed at the channel region of the barrier transfer gate TBR to inhibit any transfer of electrons therethrough, the potential .psi.RD' cannot be recovered but forms a potential well W71 having a depth of .alpha. as shown in FIG. 7, causing potential changes in output signals in following output cycles. The potential .psi.RD' is restored only by electrons transferred from the floating diffusion region 20 through many output cycles, resulting in decrease in reliability of the device.